Dual-port Static Random Access Memory (SRAM) cells can be simultaneously accessed through both ports. This means that either port of the dual-port SRAM cells can perform both read and write operations. In order for both ports of a dual-port SRAM cell to perform both read and write operations, the dual-port SRAM cells must have large access transistors for a write operation and pull-down NMOS transistors for a read operation. For this reason, conventional dual-port SRAM cells are not very scalable.
In a write operation, to write a logic 1 or HIGH to a memory cell that previously stored a logic 0, the access transistor has to pull the pull-down NMOS transistor out of the saturated state (ON state). Pulling up a saturated NMOS device requires large access transistors. Large access transistors occupy large silicon area and present large capacitive loads. For example, in a six transistor (6-T) dual-port SRAM cell, the access transistor has to be at least 10 times larger than the pull-down NMOS transistor of the memory cell. In an eight transistor (8-T) dual-port SRAM cell, the use of a complement read transistor and a complement write transistor has partially alleviated the large access transistor problems in a write operation since the complement write access transistor assists the write access transistor in pulling the saturated pull-down NMOS transistor. However, the other access transistor is still a large transistor that takes up valuable surface area and presents high capacitive loading to the memory cell.
In a read operation, large pull-down NMOS transistors are required to prevent the large access transistors from inadvertently flipping the logic state of the inverters. Accordingly, in 6-T dual-port SRAM cells, the pull-down NMOS transistors have to be at least 10 times larger than the access transistors to avoid unwanted logic state change caused by the large access transistors. Therefore, transistors in dual-port SRAM cell have to be properly sized so that a port can perform both read operation and write operation. This means that the pull-down NMOS transistors and the access transistors in conventional dual-port SRAM cells have to be large transistors, thus occupying a large silicon area and presenting large capacitive load.
Although six-transistor (6-T) dual-port SRAM cells have only six transistors instead of eight transistors, they require a write voltage control circuit to apply the correct write voltages to the first bitline and wordline. Without this write voltage control circuit write circuitry, the conventional 6-T dual-port SRAM cells will not have the correct write voltages. Furthermore, another voltage control circuit is required to reduce the voltage level on the power supply line when the write circuit applies the write voltages. The cell area of the prior art 6-T dual-port SRAM cell is reduced, but the overall silicon surface area of the dual-port SRAM array is not reduced because each cell needs the extra voltage level control circuits.
Thus, there is a need for a reduced size dual-port SRAM cell and a dual-port SRAM cell array. Also there is a need for a reduced size dual-port SRAM cell that does not require large access transistors. Furthermore, there is a need for a dual-port SRAM cell array that does not require additional voltage-level control circuitry.